View NCP6951B_8370512.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2015 november, 2015 ? rev. 0 1 publication order number: ncp6951/d NCP6951B camera pmic with flash led driver the NCP6951B integrated circuit is part of the on semiconductor mini power management ic family. it is optimized to supply battery powered portable application sub?systems such as camera function, microprocessors... etc. this device integrates one high efficiency 600 ma step?down dcdc converter with dvs (dynamic voltage scaling), 5 low dropout (ldo) voltage regulators and a 1.5 a flash led driver in wlcsp24 package. features ? one flash led driver: ? adaptive boost supply or bypass mode depending on v in and v flash conditions ? programmable flash current from 100 ma to 1.6 a by 100 ma steps ? programmable safety and inhibit timer to limit the flash duration and protect the application ? one dcdc converter: ? peak efficiency 96% ? programmable output voltage from 0.8 v to 2.3 v by 50 mv steps ? 600 ma output current capability ? five low noise ? low dropout regulators ? programmable output voltage from 1.7 v to 3.3 v for ldos 1,2,3 ? programmable output voltage from 1.2 v to 2.85 v for ldo 4 & 5 ? 200 ma output current capability: ldo?s 1, 2, 3 & 4 ? 300 ma output current capability: ldo 5 ? 45 vrms low output noise ? control ? 400 khz / 3.4 mhz i 2 c control interface ? hardware enable pin ? customizable power up sequencer ? extended input voltage range 2.5 v to 5.5 v ? support of newest battery technologies ? optimized power efficiency ? 82 a very low quiescent current at no load ? dynamic voltage scaling on dcdc converter ? regulators can be supplied from dcdc converter output ? small footprint ? package wlcsp24 2.57 x 1.65 mm 2 ? dcdc converter runs at 3.0 mhz using a 1 h inductor and 10 f capacitor or 2.2 h inductor and 4.7 f capacitor typical applications ? cellular phones ? digital cameras ? personal digital assistant and portable media player ? gps wlcsp24 case 567ja marking diagram* www. onsemi.com see detailed ordering and shipping information on page 34 o f this data sheet. ordering information (top view) a = assembly location wl = wafer lot y = year ww = work week = pb?free package 6951b awlyww *pb?free indicator, ?g? or microdot ? ?, may or may not be present. d4 d3 d5 vbg vout4 vout5 d6 c3 agnd c4 hwen c5 sda c6 pgnd1 vin2 b3 agnd b4 scl b5 fb1 b6 sw1 d2 d1 vbst fl c1 sw2 c2 flen b1 sw2 b2 flsel a3 vout2 a4 vin1 a5 vout1 a6 pvin1 a1 pgnd2 a2 vout3 pin assignment
NCP6951B www. onsemi.com 2 processor i c enabling system supply dcdc 1 out 2.2uf 10uf 1uh 1.0uf NCP6951B fb1 pvin1 sw1 pgnd1 i c power up & down sequencer thermal protection sda scl hwen dcdc 1 600ma 100nf core agnd vbg vin1 vin2 1.0uf system supply system or dcdc supply vout1 ldo1 200ma 1.0uf vout2 ldo2 200ma 1.0uf vout3 ldo3 200ma 1.0uf vout4 ldo4 200ma 1.0uf vout 5 ldo5 300ma 1uf boost converter 1.5a led driver sw2 pgnd 2 1 x 22uf 0603 or 2 x 10uf 0402 flash led vbst fl led current select enabling flash control 1.5a led driver flsel flen flash led current select pa transmit burst, torch, etc flash enable signal system or dcdc supply 1uh 4.7uf figure 1. functional block diagram
NCP6951B www. onsemi.com 3 table 1. pin out description pin name type description power a4 vin1 power input analog supply. this pin is the device analog, digital and ldo 1, 2 & 3 supply. a 1.0 f ceramic capacitor or larger must bypass this input to ground. this capacitor should be placed as close a possible to this pin. d3 vbg analog input reference voltage. a 0.1 f ceramic capacitor must bypass this pin to the ground b3, c3 agnd analog ground analog ground. analog and digital modules ground. must be connected to the system ground. control and serial interface c4 hwen digital input hardware enable. active high will enable the part; there is internal pull down resistor on this pin. b4 scl digital input i 2 c interface clock c5 sda digital input/output i 2 c interface data dcdc converter a6 pvin1 power input dcdc power supply. this pin must be decoupled to ground by a 2.2 f ceramic capacitor. this capacitor should be placed as close a possible to this pin . b6 sw1 power output dcdc switch power. this pin connects power transistors to one end of the inductor. typical ap- plication uses 1.0 h inductor; refer to application section for more information. b5 fb1 analog input dcdc feedback voltage. must be connected to the output capacitor. this is the input to the error amplifier. c6 pgnd1 power ground dcdc power ground. this pin is the power ground and carries the high switching current. high quality ground must be provided to prevent noise spikes. to avoid high?density current flow in a limited pcb track, a local ground plane is recommended. ldo regulators a4 vin1 power input ldo 1, 2 & 3 power and core supply (see power table) d5 vin2 power input ldo 4 & 5 power supply. this pin requires a 1 f decoupling capacitor. a5 vout1 power output ldo 1 output power. this pin requires a 1 f decoupling capacitor. a3 vout2 power output ldo 2 output power. this pin requires a 1 f decoupling capacitor. a2 vout3 power output ldo 3 output power. this pin requires a 1 f decoupling capacitor. d4 vout4 power output ldo 4 output power. this pin requires a 1 f decoupling capacitor. d6 vout5 power output ldo 5 output power. this pin requires a 1 f decoupling capacitor. flash led driver d1 vbst power output flash led driver boost output. this pin is the output of the boost converter. it requires a 10 f decoupling capacitor. b1, c1 sw2 power output flash led driver switch power. this pin connects power transistors to one end of the inductor. typical application uses 1.0 h inductor; refer to application section for more information. a1 pgnd2 power ground flash led driver power ground. this pin is the power ground and carries the high switching cur- rent. high quality ground must be provided to prevent noise spikes. to avoid high?density current flow in a limited pcb track, a local ground plane is recommended. d2 fl power output flash led driver output power. this pin is the output of the current source of the flash led driv- er. it needs a flash led to connect. b2 flsel logic input flash led driver select pin. active high will select the reduced flash level. c2 flen logic input flash led driver enable pin. active high will enable the flash mode.
NCP6951B www. onsemi.com 4 table 2. maximum ratings rating symbol value unit analog and power pins: avin, pvin, sw, vin1, vin2, vout1, vout2, vout3, vout4, vout5, fb, vbg pins v a ?0.3 to + 6.0 v digital pins: scl, sda, hwen pin: input voltage input current v dg i dg ?0.3 to v a +0.3 6.0 10 v ma storage temperature range t stg ?65 to + 150 c maximum junction temperature t jmax ?40 to +150 c moisture sensitivity (note 1) msl level 1 ? human body model (hbm) esd rating (note 2) esd hbm 2000 v charged device model (cdm) esd rating (note 2) esd cdm 1000 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. the thermal shutdown set to 150 c (typical) avoids potential irreversible damage on the device due to power dissipation. 2. this device series contains esd protection and passes the following ratings: human body model (hbm) per jedec standard: jesd22?a114 charged device model (cdm) per jedec standard: jesd22?c101. table 3. recommended operating conditions symbol parameter conditions min typ max unit v in1 pv in core power supply, dcdc power supply and ldos 1, 2 & 3 2.5 5.5 v v in2 ldos 4 & 5 input voltage range 1.7 5.5 v t a ambient temperature range ?40 25 + 85 c t j junction temperature range (note 6) ?40 25 +125 c r ja thermal resistance junction to case ? 80 ? c/w p d power dissipation rating (note 4) t a = 25 c ? 1250 ? mw t a = 85 c ? 500 ? mw l inductor for dcdc converter (note 4 ) 1 2.2 h co output capacitor for dcdc converter (note 4) 10 f output capacitors for ldo (note 4) 0.65 1 f c bg output capacitors for v bg 100 nf cpvin input capacitor for dcdc converter (note 4 ) 2.2 f cvin1 input capacitor for vin1 (note 4 ) 1 f cvin2 input capacitor for vin2 (note 4 ) 1 f v fl led voltage lowest torch setting i fl = 1 a i fl = 1 a 2.0 2.8 3.3 4.5 4.9 v functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. 3. moisture sensitivity level (msl): 1 per ipc/jedec standard: j?std?020a. 4. refer to the application information section of this data sheet for more details. 5. the r ca is dependent of the pcb heat dissipation. board used to drive this data was a ncp6951evb board. it is a multilayer board with 1?ounce internal power and ground planes and 2?ounce copper traces on top and bottom of the board. 6. the maximum power dissipation (p d ) is dependent by input voltage, maximum output current and external components selected. r ja 125 t a p d
NCP6951B www. onsemi.com 5 table 4. electrical characteristics min & max limits apply for t j up to +125 c unless otherwise specified. pvin = v in1 = v in2 = 3.6 v (unless otherwise noted). dcdc output voltage = 1.2v, ldo1, 2 & 4= 2.8 v, ldo 3 & 5 = 1.8 v, typical values are referenced to t j = + 25 c and default configuration (note 9). symbol parameter conditions min typ max unit supply current: pins vin1, vin2, pvin i q operating quiescent current dcdc on ? no load ? no switching ldos off t a = up to +85 c ? 32 ? a dcdc on ? no load ? no switching ldos on ? no load t a = up to +85 c ? 80 ? dcdc off ldos on ? no load t a = up to +85 c ? 55 ? i sleep product sleep mode current hwen on all dcdc and ldos off v in = 2.5 v to 5.5 v t a = up to +85 c ? 6.0 ? a i off product off current hwen off i 2 c interface disabled v in = 2.5 v to 5.5 v t a = up to +85 c ? 0.7 ? a dcdc converter pv in input voltage range 2.5 ? 5.5 v i outmax maximum output current 0.6 ? ? a vout output voltage dc error io=300 ma, pwm mode (note 9) ?1 0 1 % dc out dcdc output voltage programmable 50 mv steps (note 9) 0.8 2.3 v f sw switching frequency 2.7 3 3.3 mhz r onhs p?channel mosfet on resistance from pvin1 to sw1 pins, pvin1 = 3.6 v ? 185 ? m r onls n?channel mosfet on resistance from sw1 to pgnd1 pins, pvin1 = 3.6 v ? 335 ? m i pk peak inductor current open loop 2.5 v pv in 5.5 v 1.0 1.35 1.7 a load regulation i out from 300 ma to i outmax ? ?0.5 ? %/a line regulation i out = 100 ma 2.5 v v in 5.5 v ? 0 ? %/v d maximum duty cycle ? 100 ? % t start soft?start time from hwen to 90% of output volt- age (note 10) ? 128 s r disdcdc dcdc active output discharge ? 7.0 ? ldo1, ldo2, ldo3 v in1 ldo1, ldo2, ldo3 input voltage range 2.5 ? 5.5 v i outmax1,2,3 maximum output current 200 ? ? ma i lim1,2,3 output current limitation (note 9) ? ? 500 ma i sc1,2,3 short circuit protection ? 130 ? ma v out1,2,3 output voltage programmable, see table. (note 9) 1.7 3.3 v 7. devices that use non?standard supply voltages which do not conform to the intent i 2 c bus system levels must relate their input levels to the v dd voltage to which the pull?up resistors r p are connected. 8. refer to the application information section of this data sheet for more details. 9. guaranteed by design and characterized. 10. tested in production at v out = 2.0 v.
NCP6951B www. onsemi.com 6 table 4. electrical characteristics min & max limits apply for t j up to +125 c unless otherwise specified. pvin = v in1 = v in2 = 3.6 v (unless otherwise noted). dcdc output voltage = 1.2v, ldo1, 2 & 4= 2.8 v, ldo 3 & 5 = 1.8 v, typical values are referenced to t j = + 25 c and default configuration (note 9). symbol unit max typ min conditions parameter ldo1, ldo2, ldo3 t start1 soft?start time from hwen to 90% of output voltage (note 10) ? 128 s v out1,2,3 output voltage accuracy dc i out1,2, 3 = 200 ma ?2 v nom +2 % load regulation i out1,2, 3 = 0 ma to 200 ma ? 0.4 ? % line regulation v in1 = (vout + drop) to 5.5 v v out1,2 = 2.8 v, v out3 = 1.8 v i out1,2,3 = 200 ma ? 0.3 ? % v drop dropout voltage i out1,2,3 = 200 ma, v out = 3.3 v ? 2% 135 mv i out1,2,3 = 200 ma, v out = 2.8 v ? 2% ? 170 270 psrr ripple rejection f = 1 khz, 100 mv peak to peak v out1,2 = 2.8 v, v out3 = 1.8 v i out1,2,3 = 5 ma ? ?70 ? db f = 10 khz, 100 mv peak to peak v out1,2 = 2.8 v, v out3 = 1.8 v i out1,2,3 = 5 ma ? ?60 ? noise 10 hz 100 khz, 5 ma v out1,2,3 = 2.8 v ? 45 ? v r disldo1,2,3 ldo active output discharge ? 15 ? ldo4 and ldo5 v in2 ldo4 and ldo5 input voltage 1.7 ? 5.5 v i outmax4 maximum output current 200 ? ? ma i outmax5 maximum output current 300 ? ? ma i lim4 output current limitation (note 9) ? ? 500 ma i lim5 output current limitation (note 9) ? ? 600 ma i sc4 short circuit protection ? 130 ? ma i sc5 short circuit protection ? 180 ? ma v out4,5 ldo 4&5 output voltage programmable, see table. (note 9) 1.2 ? 2.85 v t start2 soft?start time time from i 2 c command ack to 90% of output voltage. ? 128 s v out4 output voltage accuracy i out4 = 200 ma ?2 v nom +2 % v out5 output voltage accuracy i out5 = 300 ma ?2 v nom +2 % load regulation i out4 = 0 ma to 200 ma i out5 = 0 ma to 300 ma ? 0.4 ? % line regulation v in2 = (vout + drop) to 5.5 v v out4 = 2.8 v, v out5 = 1.8 v i out4 = 200 ma, i out5 = 300 ma ? 0.3 ? % 7. devices that use non?standard supply voltages which do not conform to the intent i 2 c bus system levels must relate their input levels to the v dd voltage to which the pull?up resistors r p are connected. 8. refer to the application information section of this data sheet for more details. 9. guaranteed by design and characterized. 10. tested in production at v out = 2.0 v.
NCP6951B www. onsemi.com 7 table 4. electrical characteristics min & max limits apply for t j up to +125 c unless otherwise specified. pvin = v in1 = v in2 = 3.6 v (unless otherwise noted). dcdc output voltage = 1.2v, ldo1, 2 & 4= 2.8 v, ldo 3 & 5 = 1.8 v, typical values are referenced to t j = + 25 c and default configuration (note 9). symbol unit max typ min conditions parameter ldo4 and ldo5 v drop dropout voltage i out4 = 200 ma v out4 = 2.8 v ? 2% ? 170 270 mv i out5 = 300 ma v out5 = 2.8 v ? 2% ? 120 220 i out5 = 300 ma v out5 = 1.8 v ? 2% 250 psrr ripple rejection f = 1 khz, 100 mv peak to peak i out4= 5 ma, i out5= 5 ma ? ?70 ? db f = 10 khz, 100 mv peak to peak i out4,5= 5 ma ? ?60 ? noise 10 hz 100 khz, 5 ma v out4,5 = 2.8 v ? 45 ? v r disldo4,5 ldo 4&5 active output discharge ? 15 ? flash led driver v in input voltage pass through mode boost mode 2.8 2.8 5.5 4.5 v uvlo l uvlo low threshold i 2 c programmable with 150 mv steps (note 9) 2.75 3.2 v uvlo h uvlo high threshold i 2 c programmable with 150 mv steps (note 9) 2.9 3.35 v uvlo acc uvlo threshold accuracy ?50 50 mv v bst boost output voltage (note 9) 3.0 5.0 v v bst ? v fl driver headroom 350 mv i fl flash current i 2 c programmable with 100 ma steps (note 9) 100 1600 ma i fllow reduced current i 2 c programmable with 100 ma steps (note 9) 100 1600 ma i torch torch current i 2 c programmable with 33 ma steps (note 9) 33 533 ma i flacc flash current accuracy i fl = 300 ma 8 % i torchacc torch current accuracy i torch = 100 ma 10 % flash current slope ramp up or down 100/16 ma/ s torch current slope ramp up or down 33/16 ma/ s pa burst blanking speed from flash to reduced setting 10 s f sw boost switching frequency 1.8 2 2.2 mhz r on_h high?side mosfet on resistance 70 m r on_l low?side mosfet on resistance 60 m i lim?boost i 2 c programmable with 600 ma steps (note 9) 1.8 3.6 a i ccfl short circuit detect threshold 1.2 v 7. devices that use non?standard supply voltages which do not conform to the intent i 2 c bus system levels must relate their input levels to the v dd voltage to which the pull?up resistors r p are connected. 8. refer to the application information section of this data sheet for more details. 9. guaranteed by design and characterized. 10. tested in production at v out = 2.0 v.
NCP6951B www. onsemi.com 8 table 4. electrical characteristics min & max limits apply for t j up to +125 c unless otherwise specified. pvin = v in1 = v in2 = 3.6 v (unless otherwise noted). dcdc output voltage = 1.2v, ldo1, 2 & 4= 2.8 v, ldo 3 & 5 = 1.8 v, typical values are referenced to t j = + 25 c and default configuration (note 9). symbol unit max typ min conditions parameter hwen, flsel, flen v ih high level input voltage threshold 1.1 ? ? v v il low level voltage threshold ? ? 0.4 v i pd logic pins pull?down (input bias current) 0.1 1 a i 2 c v i2c voltage at scl and sda line 1.7 ? 5.0 v v i2cil scl, sda low input voltage scl, sda pin (note 7) ? ? 0.5 v v i2cih scl, sda high input voltage scl, sda pin (note 7) 0.8xv i 2 c ? ? v v i2col scl, sda low output voltage i sink = 3 ma ? ? 0.4 v f scl i 2 c clock frequency ? ? 3.4 mhz total device v uvlo under voltage lockout v in rising ? ? 2.5 v v uvloh under voltage lockout hysteresis v in falling 60 ? 200 mv t sd thermal shut down protection ? 150 ? c t warning warning rising edge ? 135 ? c t sdh thermal shut down hysteresis ? 15 ? c 7. devices that use non?standard supply voltages which do not conform to the intent i 2 c bus system levels must relate their input levels to the v dd voltage to which the pull?up resistors r p are connected. 8. refer to the application information section of this data sheet for more details. 9. guaranteed by design and characterized. 10. tested in production at v out = 2.0 v.
NCP6951B www. onsemi.com 9 typical characteristics figure 2. dcdc1 efficiency vs. i out (auto mode) v out = 0.8 v figure 3. dcdc1 efficiency vs. i out (auto mode) v out = 1.2 v i out (ma) iout (ma) 1000 100 10 1 0.1 50 55 60 65 70 80 85 90 1000 100 10 1 0.1 50 55 60 65 70 75 85 90 eff (%) eff (%) 75 vin = 5.5 v vin = 5.0 v vin = 4.2 v vin = 3.6 v vin = 3.2 v vin = 2.9 v vin = 2.7 v vin = 2.5 v vin = 5.5 v vin = 5.0 v vin = 4.2 v vin = 3.6 v vin = 3.2 v vin = 2.9 v vin = 2.7 v vin = 2.5 v 80
NCP6951B www. onsemi.com 10 typical characteristics figure 4. dcdc1 efficiency vs. i out (auto mode) v out = 1.8 v figure 5. dcdc1 efficiency vs. i out (auto mode) v out = 2.3 v iout (ma) iout (ma) 1000 100 10 1 0.1 50 55 65 70 80 85 90 100 1000 100 10 1 0.1 50 55 65 70 75 85 90 100 figure 6. ldo1 load regulation (v out = 2.8 v) figure 7. ldo1 load regulation (v out = 3.3 v) iout (ma) iout (ma) 250 200 150 100 50 0 ?1.0 ?0.5 0 0.5 1.0 250 200 150 100 50 0 ?1.0 ?0.5 0 0.5 1.0 figure 8. ldo1 load regulation (v out = 1.8 v) figure 9. ldo1 load regulation (v out = 1.2 v) iout (ma) iout (ma) 250 200 150 100 50 0 ?1.0 ?0.5 0 0.5 1.0 250 200 150 100 50 0 ?1.0 ?0.5 0 0.5 1.0 eff (%) eff (%) dcload (%) dcload (%) dcload (%) dcload (%) vin = 5.5 v vin = 5.0 v vin = 4.2 v vin = 3.6 v vin = 3.2 v vin = 2.9 v vin = 2.7 v vin = 2.5 v 60 75 95 vin = 5.5 v vin = 5.0 v vin = 4.2 v vin = 3.9 v vin = 3.6 v vin = 3.3 v vin = 2.9 v vin = 2.7 v 60 80 95 vin = 5.5 v vin = 5.0 v vin = 4.2 v vin = 3.6 v vin = 3.3 v vin = 3.2 v vin = 3.2 v vin = 3.0 v vin = 5.5 v vin = 5.0 v vin = 4.2 v vin = 3.9 v vin = 3.8 v vin = 3.7 v vin = 3.6 v vin = 3.5 v vin = 5.5 v vin = 5.0 v vin = 4.2 v vin = 3.6 v vin = 2.9 v vin = 2.7 v vin = 2.5 v vin = 2.3 v vin = 5.5 v vin = 5.0 v vin = 4.2 v vin = 3.6 v vin = 2.5 v vin = 1.9 v vin = 1.8 v vin = 1.7 v
NCP6951B www. onsemi.com 11 typical characteristics figure 10. ldo5 load regulation (v out = 1.2 v) figure 11. dropout voltage vs. v out , ldo1, 2 & 3 (i out = 200 ma) i out (ma) v out setting (v) 300 250 200 150 100 50 0 ?1.0 ?0.5 0 0.5 1.0 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 100 150 200 250 figure 12. dropout voltage vs. v out , ldo4 & 5 (i out = 200 ma for ldo4 and 300 ma for ldo5) figure 13. ldox psrr (v in = 3.6 v ? v out ? 1.8 v ? i out = 5 ma) v out setting (v) frequency (hz) 2.7 2.5 2.4 2.3 2.2 2.0 1.9 1.8 150 200 250 300 100,000 10,000 1000 100 ?100 ?90 ?70 ?60 ?50 ?40 ?30 0 figure 14. flash led efficiency vs. input voltage (i flash = 700 ma, v in falling) figure 15. torch led efficiency vs. input voltage (i torch = 300 ma, v in falling) vbat (v) vbat (v) 4.1 4.0 3.8 3.7 3.6 3.5 3.3 3.2 60 65 70 75 80 90 95 100 5.5 5.0 4.5 4.0 3.5 3.0 0 10 30 40 60 70 90 100 dcload (%) vdrop (mv) vdrop (mv) psrr (db) efficiency (%) efficiency (%) 3.3 ?80 ?20 ?10 2.1 2.6 2.8 3.4 3.9 4.2 85 20 50 80 350 vin = 5.5 v vin = 5.0 v vin = 4.2 v vin = 3.6 v vin = 2.5 v vin = 1.9 v vin = 1.8 v vin = 1.7 v ldo5 ldo4 ldo1 ldo2 ldo3 ldo1 ldo2 ldo3 ldo4 ldo5 ?40 c 25 c 85 c ?40 c 25 c 85 c
NCP6951B www. onsemi.com 12 detailed description the NCP6951B is optimized to supply the different sub systems of battery powered portable applications. the ic can be supplied directly from the latest technology single cell batteries such as lithium?polymer as well as from triple alkaline cells. alternatively, the ic can be supplied from a pre?regulated supply rail in case of multi?cell or mains powered applications. the output voltage range, current capabilities and performance of the switched mode dcdc converter are well suited to supply the different peripherals in the system as well as to supply processor cores. to reduce overall power consumption of the application, dynamic voltage scaling (dvs) is supported on the dcdc converter. for pwm operation, the converter runs on a local 3 mhz clock. a low power pfm mode is provided that ensures that even at low loads high efficiency can be obtained. all the switching components are integrated including the compensation networks and synchronous rectifier. small sized 1 h inductor and 10 f bypass capacitor are required for typical applications. the general purpose low dropout regulators can be used to supply the lower power rails in the application. to improve on overall application standby current, the bias current of these regulators are made very low. the regulators have two separated input supply pin to be able to connect them independently to either the system supply voltage or to the output of the dcdc converter in the application. the regulators are bypassed with a small size 1.0 f capacitor. the ic is controlled through the i 2 c interface that allows to program amongst others the output voltages of the different supply rails as well as to configure its behavior. in addition to this bus, a digital hardware enable control pin (hwen) is provided. under voltage lockout the core does not operate for voltages below the under voltage lockout (uvlo) threshold and all internal circuitry, both analog and digital, is held in reset. NCP6951B functionality is guaranteed down to v uvlo when the battery is falling. a hysteresis is implemented to avoid erratic on / off behavior of the ic. due to its 200 mv hysteresis, when the battery is rising, re?start is guaranteed at 2.5 v. thermal shutdown given the output power capabilities of the on chip step down converters and low drop out regulators the thermal capabilities of the device can be exceeded. a thermal protection circuit is therefore implemented to prevent the part from damage. this protection circuit is only activated when the core is in active mode (at least one output channel is enabled). during thermal shutdown, all outputs of NCP6951B are off. when NCP6951B returns from thermal shutdown, it can re?start in two different configurations depending on rearm[7:6] bits ($09 register). if rearm[7:6] = 00 then NCP6951B re?starts with default register values, otherwise it re?starts with register values set prior to thermal shutdown. in addition, a thermal warning is implemented which can inform the processor through an interrupt that NCP6951B is close to its thermal shutdown so that preventive action can be taken by software. active output discharge by default, to prevent any disturbances on power?up sequence, output dischar ge is activated as soon as the input voltage is valid (upper than uvlo+ hyst). after power up sequence and during on state, output discharge can be independently enabled / disabled by appropriate settings in the dis register (refer to the register definition section). if a power down sequence, uvlo or thermal shutdown events occurs, the output discharge paths are activated until the next pus and on state. when the ic is turned off when vin1 drops down below uvlo threshold, no shut down sequence is expected, all supplies are disabled and outputs turn to high impedance. enabling the hwen pin controls the device start up. if hwen is raised, this starts the power up sequencer (pus). if hwen is made low, device enters in shutdown mode and all regulators will be turned off with inverted pus of power up. a built?in pull?down resistor disables the device if this pin is left unconnected. when hwen is high, the different power rails can be independently enabled / disabled by writing the appropriate bit in the enable register. power up sequence and hwen when enabling part with hwen pin, the part will be set with the default configuration factory programmed in the registers, if no i 2 c programming has been done as described in the below table.
NCP6951B www. onsemi.com 13 table 5. default power up sequencer delay (in s) from tstart sequence default assignment default vprog default mode and on/off 128 to: 000 dcdc 1.20 v auto pfm/pwm off 256 t1: 001 ldo1 2.80 v off 384 t2: 010 ldo2 2.80 v off 512 t3: 011 ldo3 1.80 v off 640 t4: 100 ldo4 2.80 v off 768 t5: 101 ldo5 1.80 v off note: additional power sequence are available. please contact your on representative for further information. figure 16. ipus the initial power up sequence (ipus) is described in figure 16. o f f m o d e por uvlo hwen (dcdc_t[2:0] + 1) x 128 s * dvs ramp time 600 us typ vin1, vin2 vout dcdc soft start90% bias time (ldox_t[2:0] + 1) x 128 s * vout ldox 128 us i c figure 17. ipus in order to power up the circuit, the input voltage vin1 has to rise above the vuvlo threshold. this triggers the internal core circuitry power up including: ? internal references ? core circuitry ?wake up time? ? dcdc ?bias time? these delays are internals and cannot be bypassed. as the default configuration factory is programmed with disable state for the dcdc and ldos, an i 2 c access must be done at the end of the bias time to enable the supplies. in addition a user programmable delay will also take place between end of core circuitry turn on (bias time) and start up time: the powersupplies_t [2..0] bits of time register will set this user programmable delay with a 128 s resolution (note: please contact your on semiconductor representative for additional resolution options). the output discharge of the dcdc and ldos are done during this time slot. note: during the bias time, the i 2 c interface is not active during the first 50 s. any i 2 c request to the ic during this time period will result in a nack reply. however, i 2 c registers can be read and written while hwen pin is still low (except blanking time of 50 s typical). by programming the appropriate registers (see registers description section), the power up sequence default can be modified and set upon requirements (please contact your on semiconductor representative for additional pus options)
NCP6951B www. onsemi.com 14 o f f m o d e por uvlo hwen (dcdc_t[2:0] + 1) x 128 s * dvs ramp time 70 us typ vin1, vin2 vout dcdc soft start90% bias time (ldox_t[2:0] + 1) x 128 s * vout ldox 128 us i c s l e e p m o d e 600 s min figure 18. sleep mode pus (smpus) a third turn on sequence is also available by i 2 c. indeed each power supply can be turn off/on through i 2 c register. in this case no biasing time is required except for dcdc bias time (32 s typical). por uvlo hwen dvs ramp time vin1, vin2 vout dcdc soft start 90% vout ldox 128 us i c ldox, dcdc off/ on bias time 32 s figure 19. on mode pus (opus) shutdown by hwen when hwen is tied low, all supplies are disabled with reverted turn on sequence detailed in default power up sequencer table. if different turn off sequence is required, a different programming can be done by i 2 c. dcdc converter the converter can operate in two modes: pwm mode and pfm mode. in pwm mode the converter operates at a fixed frequency and adapts its duty cycle to regulate to the desired output voltage. the advantage of this mode is that the emi noise is predictable. however, at lower loadings the efficiency is degraded. in pfm mode some switching pulses are skipped to control the output voltage. this allows maintaining high efficiency even at low loadings. in addition, no high frequency clock is required which provides additional current savings. the switchover point between both modes is chosen depending on the supply conditions such that highest efficiency is obtained over the entire load range. the switch over between pwm/pfm modes can occur automatically but the switcher can be set in auto switching mode pfm / pwm by i 2 c programming. a soft start is provided to limit inrush currents when enabling the converters. the soft start consists of ramping gradually the reference to the switcher. additional current limitation is provided by a peak current limiter that monitors and limits the current through the inductor. dcdc converter output voltage can be set by i 2 c modedcdc bit is used to program switcher mode control. table 6. modedcdc bit description modedcdc dcdc mode control 0 mode is auto switching pfm / pwm (default) 1 mode is pwm only dynamic voltage scaling (dvs) step down converters support dynamic voltage scaling (dvs). this means the output voltage can be reprogrammed based upon i 2 c commands to provide the different voltages required by the processor. the change between set points is managed in a smooth manner without disturbing the operation of the processor. when programming a higher voltage, the reference of the switcher and therefore the output is raised in 50 mv/ 2.67 s (default) steps such that the dv/dt is controlled. when programming a lower voltage the output voltage will decrease based on the output capacitor value and the load. the dvs system makes sure that the voltage ramp down will not exceed the steps settings. v2 internal reference output voltage t v figure 20. dynamic voltage scaling effect timing figure 21. dvs figure
NCP6951B www. onsemi.com 15 programmability dcdc converter has two different output voltages programmed by default in the dcdc_v1 and v2 bank. the dcdc output voltage can be changed from v1 to v2 with the dcdc_v2/v1 bit in $08 register. table 7. dcdc_v2/1 bit description dcdc_v2/1 bit description 0 output voltage is set to dcdc_v2 1 output voltage is set to dcdc_v1(default) the two dvs bits in register time determine ramp up time per each voltage step. table 8. dvs bit description dvs [0] bit description 0 2.67 s per step (default) 1 10.67 s per step dcdc step down converter and ldos end of turn on sequence to indicate the end of the power up sequence, a power good sense bit is available at the $0a address. (sen_pg). sense bit is set to 0 during power up sequence and 16 x digital clock (128?s by default). the power good sense bit is released to 1 after this sequence and trig ack_pg interrupt. the interrupt is reset by a read or hwen. figure 22. power good behavior interrupt the interrupt controller continuously monitors internal interrupt sources, generating an interrupt signal when a system status change is detected (dual edge monitoring). the interrupt sources include: table 9. interrupt sources register $0b uvlo under voltage threshold pus end of power up sequence wnrg thermal warning tsd thermal shutdown individual bits generating interrupts will be set to 1 in the int_ack register (i 2 c read only register), indicating the interrupt source. int_ack register is reset by an i 2 c read. int_sen registers (read only registers) are real time indicators of interrupt sources. force register reset the i 2 c registers are reset when the part is in off mode: ? vinNCP6951B includes an adaptive boost converter with an high side current source allowing the use of a thermally grounded flash led. flash led driver has two mains operating modes: flash mode and torch mode which is controlled thru the i 2 c interface and the flen and flsel pins. adaptive boost ? bypass converter NCP6951B includes an adaptive boost?bypass converter to optimize the efficiency of the flash led driver. the boost?bypass converter monitors the flash led voltage and the battery voltage. when v bst < v fl + 250 mv, the adaptive boost?bypass converter operates in boost mode and regulates v bst = v fl + 275 mv. when v bat v fl + 540 mv, the adaptive boost?bypass converter operates in bypass mode and v bst = v bat . boost mode the adaptive boost?bypass converter implements an architecture allowing the device to operate in continuous conduction mode (ccm) and discontinuous conduction mode (dcm). the adaptive boost?bypass converter operates in dcm in order to save power and improve efficiency at low loads by reducing the switching frequency. when current in the inductor becomes continuous, the controller automatically turns to ccm mode and goes back in dcm when current in the inductor is discontinuous. bypass mode the adaptive boost?bypass converter has been designed to manage conditions for which v bat becomes close to v fl + 275 mv. in that case the adaptive boost?bypass converter enters automatically in bypass mode from boost mode. the v bst voltage is the copy of the input voltage minus a dropout voltage resulting from the resistance of the internal p?mosfet plus the inductor. timeout description NCP6951B includes 2 timers which help to prevent any damage to the part due to too high flash duration or too close consecutive flash. the 3 bits safety_timer[2:0] set a maximum flash duration from 32 ms to 1024 ms.
NCP6951B www. onsemi.com 16 the 4 bits inhibit_timer[3:0] register set a minimum off time duration after the flash from 0 to 7680 ms. when flen is going high, safety_timer is started and the flash current source is turn off if flen pin is not pulling down before the end of the timer. the timer is reset when flen is going low. after a flash pulse, the flash current source can remain disabled for a guaranteed off period and as such will ignore the state of the flen pin. fl_en i_led timeout safety timer inhibit timer valid flash inhibit timer prevents flash flash duration limited by safety timer figure 23. battery voltage adaptive mode behavior pa burst blanking when the flash is enabled and the flsel pin being pulled high, the reduced flash led current is selected. normally the reduced led current level is programmed much lower than the flash led current so that flsel high selects the reduced level. a dedicated bit is available to invert the polarity of the flsel pin. during pa burst blanking, the transition to the lower current is instantaneity. the transition to the higher current follow the ramp time set in the flash_setting register. fl_en v_in i_led reduced flash level normal flash level fl_sel pa burst figure 24. battery voltage adaptive mode behavior low battery protection and die temperature management in flash mode the battery voltage is permanently monitored. 2 dif ferent behaviors can be set with the battery_voltage_mode bit. low battery voltage adaptive mode: 2 thresholds can be programmed thru i 2 c to reduce the flash current in case the battery voltage is too low. when vin goes below uvlo_high, the NCP6951B try to recover by decreasing the current down to i reduced, and then increase it up to the i fl fault ? 1. flen i flash or i torch vin uvlo _h nfault nfault ? 1 nfault ? 2 nfault ? 3 t debounce i reduced figure 25. battery voltage adaptive mode behavior when vin goes below uvlo low, flash current is stopped. low battery voltage reduce mode: 2 thresholds can be programmed thru i 2 c to reduce the flash current in case the battery voltage is too low. when vin goes below uvlo_high, i flash is decreased down to i reduced. when vin goes below uvlo low, flash current is stopped. v_in i_led undervoltage high undervoltage low reduced flash level normal flash level disabled disable operation fl_en figure 26. battery voltage reduce mode behavior the die temperature is also permanently monitored. and 2 different behaviors can also be set with the die_temp_mode bit.
NCP6951B www. onsemi.com 17 die temperature management adaptative mode : flen i flash t nfault nfault ? 1 nfault ? 2 nfault ? 3 i reduced 135 c 125 c figure 27. die temperature adaptative mode behavior die temperature management reduce mode: warning (125 c ) low (135 c ) high (145 c ) disabled reduced normal figure 28. die temperature reduce mode behavior the following state machine describe the behavior of the part with the combination of the 4 monitoring modes: flash ready bit flash _en i flash flen = 0 || timeout flen = 1 && / tsd high && / uvlo _l i reduced ifl= ifl fault ? 1 ramp i up to i flash 0a flen = 0 || timeout (flen = 0 || timeout ) && /tsd high && /uvlo _l uvlo _h || tsd low uvlo _l || tsd high i = i flash /uvlo _h && / tsd low uvlo _l || tsd high uvlo _l || tsd high flen = 0 || timeout startup por low battery adaptative mode and die temperature management adaptative mode figure 29. state machine battery voltage and die temperature adaptative mode flash ready bit flash _en i flash flen = 0 || timeout flen = 1 && / tsd high && / uvlo _l i reduced ifl= ifl fault ? 1 ramp i up to i flash 0a flen = 0 || timeout (flen = 0 || timeout ) && /tsd high && /uvlo _l uvlo _h || tsd low uvlo _l || tsd high i = i flash /uvlo _h uvlo _l || tsd high uvlo _l || tsd high flen = 0 || timeout startup por low battery adaptative mode and die temperature management reduce mode figure 30. state machine battery voltage adaptative mode and die temperature reduce mode flash ready bit flash _en i flash flen = 0 || timeout flen = 1 && / tsd high && / uvlo _l i reduced ifl= ifl fault ? 1 ramp i up to i flash 0a flen = 0 || timeout (flen = 0 || timeout ) && /tsd high && /uvlo _l uvlo _h || tsd low uvlo _l || tsd high i = i flash /tsd low uvlo _l || tsd high uvlo _l || tsd high flen = 0 || timeout startup por low battery reduce mode and die temperature management adaptative mode figure 31. state machine battery voltage reduce mode and die temperature adaptative mode flash ready bit flash _en i flash flen = 0 || timeout flen = 1 && / tsd high && / uvlo _l i reduced 0a (flen = 0 || timeout ) && /tsd high && /uvlo _l uvlo _h || tsd low uvlo _l || tsd high uvlo _l || tsd high flen = 0 || timeout startup por low battery reduce mode and die temperature management reduce mode figure 32. state machine battery voltage mode and die temperature reduce mode
NCP6951B www. onsemi.com 18 low battery protection in torch mode in case of torch mode, when uvlo_l threshold is reached, the torch current is set to 0 ma and the uvlo flag is set. NCP6951B recovers its torch current when vin reach uvlo_h if the torch_retry bit is set. torch enable v_in i_led undervoltage high undervoltage low torch level disabled i_led torch level disabled disable operation retry operation figure 33. battery voltage reduce mode behavior anti red?eye function NCP6951B includes an anti red?eye function. pre?flash level and number of pre?flash pulses can be set thru the red_eye register . the user has only to send the sequence with the flen pin. a time out can be activated (2 s) in case a fl_en pulse is not sent after the first pulse to reset the function. i_led preflash level normal flash level fl_en set for up to 3 pre flashes, set duration, set the preflash level figure 34. anti red?eye behavior i 2 c compatible interface NCP6951B can support a subset of i 2 c protocol, below are detailed introduction for i 2 c programming. i 2 c communication description on semiconductor communication protocol is a subset of i 2 c protocol. figure 35. general protocol description the first byte transmitted is the chip address (with lsb bit sets to 1 for a read operation, or sets to 0 for a write operation). then the following data will be: ? in case of a write operation, the register address (@reg) we want to write in followed by the data we will write in the chip. the writing process is incremental. so the first data will be written in @reg, the second one in @reg + 1... the data are optional. ? in case of read operation, the NCP6951B will output the data out from the last register that has been accessed by the last write operation. like writing process, reading process is an incremental process. read out from part the master will first make a ?pseudo write? transaction with no data to set the internal address register. then, a stop then start or a repeated start will initiate the read transaction from the register address the initial write transaction has set:
NCP6951B www. onsemi.com 19 figure 36. read out from part the first write sequence will set the internal pointer on the register we want access to. then the read transaction will start at the address the write transaction has initiated. transaction with real write then read 1. with stop then start figure 37. write followed by read transaction write in part write operation will be achieved by only one transaction. after chip address, the mcu first data will be the internal register we want access to, then following data will be the data we want to write in reg, reg + 1, reg + 2,..., reg +n. write n registers: figure 38. write in n registers
NCP6951B www. onsemi.com 20 i 2 c address NCP6951B has fixed i 2 c but different i 2 c address (by default $10, 7 bit address, see below table a7~a1), NCP6951B supports 7?bit address only. table 10. NCP6951B i 2 c address i 2 c address hex a7 a6 a5 a4 a3 a2 a1 a0 add0 (default) w $20 /r $21 0 0 1 0 0 0 0 x address $10 0 0 1 0 0 0 0 ? different default address is available upon request register map following register map describes i 2 c registers. registers can be: reserved address is reserved and register is not physically designed spare address is reserved and register is physically designed table 11. registers summary address register name type default function $00 general_settings rw $00 dvs control settings $01 ldo1_settings rw $39 ldo1 register settings $02 ldo2_settings rw $59 ldo2 register settings $03 ldo3_settings rw $6c ldo3 register settings $04 ldo4_settings rw $9e ldo4 register settings $05 ldo5_settings rw $b1 ldo5 register settings $06 dcdc_settings1 rw $09 dcdc register settings 1 $07 dcdc_settings2 rw $07 dcdc register settings 2 $08 enable rw $80 enable and dvs register settings $09 pulldown rw $3f active discharge and rearming register $0a status r $04 status or sense register $0b interrupt_ack rc $00 interrupt register $0c flash_setting rw $1f flash current register $0d reduced_current rw $00 reduced current register $0e torch_current rw $00 torch current register $0f protection rw $20 boost peak inductor current and uvlo register $10 flash_timer rw $13 safety timer register $11 red_eye rw $43 red eye register $12 flash_configuration rw $08 flash configuration register $13 flash_enable rw $00 flash enable register $14 flash_status rc $00 flash status register $15 to $ff ? ? ? reserved. do not access to those registers details of the registers are in the following section.
NCP6951B www. onsemi.com 21 registers description table 12. general_settings register name: general_settings address: $00 type: rw default: $00 d7 d6 d5 d4 d3 d2 d1 d0 spare=0 spare=0 spare=0 dvs spare=0 spare=0 spare=0 spare=0 table 13. bit description of general_settings register bit bit description dvs[0] ramp up time per voltage step table 14. ldo1_settings register name: ldo1_settings address: $01 type: rw default: $39 d7 d6 d5 d4 d3 d2 d1 d0 ldo1_t [2:0] ldo1_v[4:0] table 15. bit description of ldo1_settings register bit bit description ldo1_v[4:0] ldo1 output voltage setting, refer to table 17 ldo1_t[2:0] ldo1 startup delay time setting (delay time between hwen transitions from low to high and ldo1 startup delay time = (ldo1_t[2:0] + 1) * 128 s note: 64 s, 128 s, 1ms, 2 ms otp options (128 s default value) table 16. ldo2_settings register name: ldo2_settings address: $02 type: rw default: $59 d7 d6 d5 d4 d3 d2 d1 d0 ldo2_t [2:0] ldo2_v[4:0] table 17. bit description of ldo2_settings register bit bit description ldo2_v[4:0] ldo2 output voltage setting, refer to table 17 ldo2_t[2:0] ldo2 startup delay time setting (delay time between hwen transitions from low to high and ldo2 startup delay time = (ldo2_t[2:0] + 1) * 128 s table 18. ldo3_settings register name: ldo3_settings address: $03 type: rw default: $6c d7 d6 d5 d4 d3 d2 d1 d0 ldo3_t [2:0] ldo3_v[4:0] table 19. bit description of ldo3_settings register bit bit description ldo3_v[4:0] ldo3 output voltage setting, refer to table 17 ldo3_t[2:0] ldo3 startup delay time setting (delay time between hwen transitions from low to high and ldo3 startup delay time = (ldo3_t[2:0] + 1) * 128 s
NCP6951B www. onsemi.com 22 table 20. ldo1_v[4:0], ldo2_v[4:0], ldo3_v[4:0] setting table register vout(v) register vout(v) register vout(v) register vout(v) 00000 1.70 01000 1.70 10000 2.10 11000 2.75 00001 1.70 01001 1.70 10001 2.20 11001 2.80 00010 1.70 01010 1.70 10010 2.30 11010 2.85 00011 1.70 01011 1.75 10011 2.40 11011 2.90 00100 1.70 01100 1.80 10100 2.50 11100 2.95 00101 1.70 01101 1.85 10101 2.60 11101 3.00 00110 1.70 01110 1.90 10110 2.65 11110 3.10 00111 1.70 01111 2.00 10111 2.70 11111 3.30 table 21. ldo4_settings register name: ldo4_settings address: $04 type: rw default: $9e d7 d6 d5 d4 d3 d2 d1 d0 ldo4_t [2:0] ldo4_v[4:0] table 22. bit description of ldo4_settings register bit bit description ldo4_v[4:0] ldo4 output voltage setting, refer to table 22 ldo4_t[2:0] ldo4 startup delay time setting (delay time between hwen transitions from low to high and ldo4 startup delay time = (ldo4_t[2:0] + 1) * 128 s table 23. ldo5_settings register name: ldo5_settings address: $05 type: rw default: $b1 d7 d6 d5 d4 d3 d2 d1 d0 ldo5_t [2:0] ldo5_v[4:0] table 24. bit description of ldo5_settings register bit bit description ldo5_v[4:0] ldo5 output voltage setting, refer to table 22 ldo5_t[2:0] ldo5 startup delay time setting (delay time between hwen transitions from low to high and ldo5 startup delay time = (ldo5_t[2:0] + 1) * 128 s table 25. ldo4_v[4:0], ldo5_v[4:0] setting table register vout(v) register vout(v) register vout(v) register vout(v) 00000 1.20 01000 1.35 10000 1.75 11000 2.40 00001 1.20 01001 1.40 10001 1.80 11001 2.50 00010 1.20 01010 1.45 10010 1.85 11010 2.60 00011 1.20 01011 1.50 10011 1.90 11011 2.65 00100 1.20 01100 1.55 10100 2.00 11100 2.70 00101 1.20 01101 1.60 10101 2.10 11101 2.75 00110 1.25 01110 1.65 10110 2.20 11110 2.80 00111 1.30 01111 1.70 10111 2.30 11111 2.85
NCP6951B www. onsemi.com 23 table 26. dcdc_settings1 register name: dcdc_settings1 address: $06 type: rw default: $09 d7 d6 d5 d4 d3 d2 d1 d0 dcdc_t[2:0] dcdc_v1[4:0] table 27. bit description of dcdc_settings1 register bit bit description dcdc_v1[4:0] dcdc output voltage setting 1, refer to table 26 dcdc_t[2:0] dcdc startup delay time setting (delay time between hwen transitions from low to high and dcdc startup delay time = (dcdc_t[2:0] + 1) * 128 s table 28. dcdc_settings2 register name: dcdc_settings2 address: $07 type: rw default: $07 d7 d6 d5 d4 d3 d2 d1 d0 spare=0 spare=0 modedcdc dcdc_v2[4:0] table 29. bit description of dcdc_settings2 register bit bit description dcdc_v2[4:0] dcdc output voltage setting 2, refer to table 26 modedcdc dcdc operating mode 0: auto switching pfm / pwm (default) 1: forced pwm table 30. dcdc_vx[4:0] setting table dcdc_v1/2 vout(v) dcdc_v1/2 vout(v) dcdc_v1/2 vout(v) dcdc_v1/2 vout(v) 00000 0.80v 01000 1.15v 10000 1.55v 11000 1.95v 00001 0.80v 01001 (v1)* 1.20v 10001 1.60v 11001 2.00v 00010 0.85v 01010 1.25v 10010 1.65v 11010 2.05v 00011 0.90v 01011 1.30v 10011 1.70v 11011 2.10v 00100 0.95v 01100 1.35v 10100 1.75v 11100 2.15v 00101 1.00v 01101 1.40v 10101 1.80v 11101 2.20v 00110 1.05v 01110 1.45v 10110 1.85v 11110 2.25v 00111 1.10v 01111 (v2) 1.50v 10111 1.90v 11111 2.30v *default value: v1 table 31. enable register name: enable address: $08 type: rw default: $80 d7 d6 d5 d4 d3 d2 d1 d0 dcdc_v2/v1 spare=0 dcdc_ en ldo5_ en ldo4_ en ldo3_ en ldo2_ en ldo1_ en
NCP6951B www. onsemi.com 24 table 32. bit description of enable register bit bit description dcdc_v2/v1 dcdc output voltage setting 0: dcdc converter output voltage is set to dcdc_v2 1: dcdc converter output voltage is set to dcdc_v1 dcdc_ en dcdc enabling 0: disabled 1: enabled ldo5_ en ldo5 enabling 0: disabled 1: enabled ldo4_ en ldo4 enabling 0: disabled 1: enabled ldo3_ en ldo3 enabling 0: disabled 1: enabled ldo2_ en ldo2 enabling 0: disabled 1: enabled ldo1_ en ldo1 enabling 0: disabled 1: enabled table 33. pulldown register name: pulldown address: $09 type: rw default: $3f d7 d6 d5 d4 d3 d2 d1 d0 rearm_ tsd[7] rearm_tsd[7] rearm_ tsd[6] dcdc_ pulldown ldo5_ pulldown ldo4_ pulldown ldo3_ pulldown ldo2_ pulldown ldo1_ pulldown table 34. bit description of pulldown register bit bit description rearm_ tsd[7:6] device rearming after thermal shut down 11: n/a 10: no re?arming after tsd 01: re?arming active after tsd with no reset of i 2 c registers: new power?up sequence is initiated with i 2 c registers values. 00: re?arming active after tsd with reset of i 2 c registers: new power?up sequence is initiated with de- fault i 2 c registers values (default). dcdc_ pulldown dcdc active output discharge 0: disabled 1: enabled ldo5_ pulldown ldo5 active output discharge 0: disabled 1: enabled ldo4_ pulldown ldo4 active output discharge 0: disabled 1: enabled ldo3_ pulldown ldo3 active output discharge 0: disabled 1: enabled ldo2_ pulldown ldo2 active output discharge 0: disabled 1: enabled ldo1_ pulldown ldo1 active output discharge 0: disabled 1: enabled
NCP6951B www. onsemi.com 25 table 35. status register name: status address: $0a type: r default: $04 d7 d6 d5 d4 d3 d2 d1 d0 spare=0 spare=0 spare=0 spare=0 sen_uvlo sen_/pus sen_tsd sen_wnrg table 36. bit description of status register bit bit description sen_uvlo uvlo sense 0: input voltage is higher than (uvlo + hyst) threshold. 1: input voltage is lower than (uvlo) threshold. sen_pus power up sequence 0: power up sequence on going 1: power up sequence finished or hwen is low sen_tsd thermal shut down sense 0: ic temperature is below tsd threshold 1: ic temperature is over tsd threshold sen_wnrg thermal warning sense 0: ic temperature is below thermal warning threshold 1: ic temperature is over thermal warning threshold table 37. interrupt_ack register name: interrupt_ack address: $0b type: rc default: $00 d7 d6 d5 d4 d3 d2 d1 d0 spare=0 spare=0 spare=0 spare=0 ack_uvlo ack_pus ack_tsd ack_wnrg table 38. bit description of interrupt_ack register bit bit description ack_uvlo uvlo sense acknowledge 0: cleared 1: sen_uvlo dual edge triggered interrupt ack_pus power up sequence sense acknowledge 0: cleared 1: sen_pus rising edge triggered interrupt ack_tsd thermal shut down sense acknowledge 0: cleared 1: sen_tsd dual edge triggered interrupt ack_wnrg thermal warning sense acknowledge 0: cleared 1: sen_wnrg dual edge triggered interrupt note: sen_pus rising edge appears (16) x 128 s (default) after hwen rising edge. table 39. flash_setting register name: flash_current address: $0c type: rw default: $1f d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 flash_tr[1:0] flash_current[4:0]
NCP6951B www. onsemi.com 26 table 40. bit description of flash_setting register bit bit description flash_current[4:0] defines the flash current. flash_tr[1:0] defines the flash ramp time. table 41. bit description of flash_current[4:0] register value flash_current[4:0] (ma) register value flash_current[4:0] (ma) 00000 100 10000 800 00001 133 10001 900 00010 166 10010 1000 00011 200 10011 1100 00100 233 10100 1200 00101 266 10101 1300 00110 300 10110 1400 00111 333 10111 1500 01000 366 11000 1600 01001 400 11001 1600 01010 433 11010 1600 01011 466 11011 1600 01100 500 11100 1600 01101 533 11101 1600 01110 600 11110 1600 01111 700 11111 1600 table 42. bit description of flash_tr[1:0] register value flash_tr[1:0] (v) 00 100 ma / 16 s 01 100 ma / 32 s 10 100 ma / 64 s 11 100 ma / 128 s table 43. reduced_current register name: flash_current address: $0d type: rw default: $00 d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 spare = 0 spare = 0 spare = 0 reduced_current[3:0] table 44. bit description of reduced_current register bit bit description reduced_current[3:0] defines the reduced current.
NCP6951B www. onsemi.com 27 table 45. bit description of reduced_current[3:0] register value reduced_current[3:0] (ma) 0000 100 0001 200 0010 300 0011 400 0100 500 0101 600 0110 700 0111 800 1000 900 1001 1000 1010 1100 1011 1200 1100 1300 1101 1400 1110 1500 1111 1600 table 46. torch_current register name: torch_current address: $0e type: rw default: $00 d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 spare = 0 torch_tr[1:0] torch_current[3:0] table 47. bit description of torch_current register bit bit description torch_current[3:0] defines the torch current. torch_tr[1:0] defines the torch ramp time. table 48. bit description of torch_tr[1:0] register value torch_tr[1:0] (v) 00 33 ma / 64 s 01 33 ma / 128 s 10 33 ma / 256 s 11 33 ma / 512 s table 49. bit description of torch_current[3:0] register value torch_current[3:0] (ma) 0000 33 0001 66 0010 100 0011 133 0100 166 0101 200 0110 233 0111 266 1000 300 1001 333 1010 366 1011 400 1100 433 1101 466 1110 500 1111 533
NCP6951B www. onsemi.com 28 table 50. protection register name: uvlo address: $0f type: rw default: $20 d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 spare = 0 ilim[1:0] uvlo_high[1:0] uvlo_low[1:0] table 51. bit description of protection register bit bit description uvlo_low[1:0] defines the uvlo low threshold. uvlo_high[1:0] defines the uvlo high threshold. ilim_cur- rent[1:0] defines the boost peak inductor cur- rent. table 52. bit description of uvlo_low[1:0] register value uvlo_low[1:0] (v) 00 2.75 01 2.9 10 3.05 11 3.2 table 53. bit description of uvlo_high[1:0] register value uvlo_high[1:0] (v) 00 2.9 01 3.05 10 3.2 11 3.35 table 54. bit description of ilim_current[1:0] register value ilim[2:0] (a) 00 1.8 01 2.4 10 3.0 11 3.6 table 55. flash_timer register name: safety_timer address: $10 type: rw default: $13 d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 inhibit_timer[3:0] safety_timer[2:0] table 56. bit description of flash_timer register bit bit description safety_timer[2:0] defines the safety timing. (maximum flash duration) inhibit_timer[3:0] defines the inhibit timing. (off duration after a flash) table 57. bit description of safety_timer[4:0] bit[2:0] safety_timer (ms) $0 32 $1 64 $2 128 $3 256 $4 512 $5 1024
NCP6951B www. onsemi.com 29 table 58. bit description of inhibit_timer[4:0] bit[3:0] inhibit_timer(ms) $00 512 $01 1024 $02 1536 $03 2048 $04 2560 $05 3072 $06 3584 $07 4096 $08 4608 $09 5120 $0a 5632 $0b 6144 $0c 6656 $0d 7168 $0e 7680 $0f 8192 table 59. red_eye register name: red_eye address: $11 type: rw default: $43 d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 red_eye_timeout pre_flash_current[3:0] pre_flash_count[1:0] table 60. bit description of red_eye register bit bit description pre_flash_count[1:0] set the number of preflash pulses. pre_flash_current[3:0] set the preflash current. red_eye_timeout activate or disactivate the timeout protection (2 s) between each pulses of the red eye functionality (preflash and flash pulses) table 61. bit description of pre_flash_count[1:0] register value pre_flash_count 00 0 01 1 10 2 11 3
NCP6951B www. onsemi.com 30 table 62. bit description of pre_flash_current[3:0] register value pre_flash_current[3:0] (ma) 0000 100 0001 200 0010 300 0011 400 0100 500 0101 600 0110 700 0111 800 1000 900 1001 1000 1010 1100 1011 1200 1100 1300 1101 1400 1110 1500 1111 1600 table 63. flash_configuration register name: flash_enable address: $12 type: rw default: $08 d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 spare = 0 spare =0 spare = 0 flsel_pol torch_retry bat_v_sel die_temp_sel table 64. bit description of flash_configuration register bit bit description die_temp_sel select the low battery voltage mode. (0 = reduce mode, 1 = adaptative mode) bat_v_sel select the die temperature monitoring mode. (0 = reduce mode, 1 = adaptative mode) torch_retry enable the retry operation for the torch low battery monitoring function. flsel_pol select the polarity of the flsel pin (0 = active low, 1 = active high) table 65. flash_enable register name: flash_enable address: $13 type: rw default: $00 d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 spare = 0 spare = 0 red_eye_en inhibit_en safety_en torch_en flash_en table 66. bit description of flash_enable register bit bit description flash_en enable the flash mode. (flash is turn on when flen pin goes high) torch_en enable the torch mode. safety_en enable the safety timer functionality. inhibit_en enable the inhibit timer functionality.
NCP6951B www. onsemi.com 31 table 67. flash_status register name: flash_status address: $14 type: rc default: $00 d7 d6 d5 d4 d3 d2 d1 d0 torch_uvlo flash_die_temp flash_pa_burst flash_uvlo flash_ovp flash_sc flash_tsd flash_timeout table 68. bit description of flash_status register bit bit description flash_timeout indicates a flash timeout event. flash_tsd indicates a flash tsd fault. flash_sc indicates a short circuit fault. flash_ovp indicates an ovp fault. flash_uvlo indicates a flash uvlo event. flash_pa_burst indicates a pa burst blanking event. flash_die_temp indicates a flash tsd warning event. torch_uvlo indicates a torch uvlo_l event.
NCP6951B www. onsemi.com 32 application information processor i c enabling system supply dcdc1 out 2.2 uf 10uf 1uh 1.0uf ncp 6951b fb pvin sw pgnd i c power up / down sequencer thermal protection sda scl hwen dcdc 1 600 ma 100nf core agnd vbg vin1 vin2 1uf system supply system supply or dcdc out vout 1 ldo 1 200 ma 1.0uf vout 2 ldo 2 200 ma 1.0uf vout 3 ldo 3 200 ma 1.0uf vout 4 ldo 4 200 ma 1.0uf vout 5 ldo 5 300 ma 1uf boost converter 1.5a led driver sw2 pgnd2 1 x 22 uf 0603 or flash led vbst fl led current select enabling flash control 1.5a led driver flsel flen flash led current select pa transmit burst , torch , etc flash enable signal battery supply 1uh 4.7 uf figure 39. typical application schematic 2 x 10 uf 0402 inductor selection NCP6951B dcdc converters typically use 1 h inductor. use of different values can be considered to optimize operation in specific conditions. the inductor parameters directly related to device performances are saturation current, dc resistance and inductance value. the inductor ripple current ( il) decreases with higher inductance. i l v o 1 v o v in l f sw (eq. 1) i lmax i omax i l 2 (eq. 2) with: ? fsw = switching frequency (typical 3 mhz) ? l = inductor value ? i l = peak?t o?peak inductor ripple current ? i lmax = maximum inductor current to achieve better efficiency, ultra low dc resistance inductor should be selected. the saturation current of the inductor should be higher than the i lmax calculated with the above equations.
NCP6951B www. onsemi.com 33 table 69. inductor l = 1.0 h supplier part # size (mm) (l x l x t) dc rated current (a) dcr max at 25 c (m ) toko dfe201610r?1r0m 2.0 x 1.6 x 1.0 2.2 66 toko dfe252012r?1r0m 2.5 x 2.0 x 1.2 3.4 38 toko dfe252012p?1r0m 2.5 x 2.0 x 1.2 3.8 35 murata lqh44pn?1r0np0 4.0 x 3.5 x 1.8 2.5 36 murata lqm2hpn?1r0mg0 2.5 x 2.0 x 1.0 1.6 69 toko fdsd0412?h?1r0m 4.2 x 4.2 x 1.2 4.7 37 output capacitor selection for dc to dc converters selecting the proper output capacitor is based on the desired output ripple voltage. NCP6951B dcdc converters typically use 10 f output capacitor. ceramic capacitors with low esr values will have the lowest output ripple voltage and are strongly recommended. the output capacitor requires either an x7r or x5r dielectric. the output ripple voltage in pwm mode can be estimated by: v o v o 1 v o v in l f sw 1 2 c o f esr (eq. 3) table 70. recommended output capacitor for dc to dc converters manufacturer part number case size height typ. [mm] c [ f] murata grm188r60j106me47 0603 0.8 10 murata grm188r60j226mea0 0603 0.8 22 tdk c1608x5r0c106k/m 0603 0.8 10 tdk c1005x5r0j106m050bc 0402 0.5 10 tdk c1608x5r0j226m080ac 0603 0.8 22 input capacitor selection for dc to dc converters in pwm operating mode, the input current is pulsating with large switching noise. using an input bypass capacitor can reduce the peak current transients drawn from the input supply source, thereby reducing switching noise significantly. the maximum rms current occurs at 50% duty cycle with maximum output current, which is 1/2 of maximum output current. a low profile ceramic capacitor of 4.7 f should be used for most of the cases. for effective bypass results, the input capacitor should be placed as close as possible to pvin1 and pvin2 pins. table 71. recommended input capacitor for dc to dc converters supplier part number case size height typ. [mm] c [uf] murata grm188r60j475ke 0603 0.8 4.7 murata grm188r60j106me 0603 0.8 10 tdk c1608x5r0c475k/m 0603 0.8 4.7 tdk c1608x5r0c106k/m 0603 0.8 10
NCP6951B www. onsemi.com 34 output capacitor for ldos for stability reason, a typical 1 f ceramic output capacitor is suitable for ldos. the ldo output capacitor should be placed as close as possible to the NCP6951B output pin. input capacitor for ldos NCP6951B ldos do not require specific input capacitors. however, a typical 1 f ceramic capacitor placed close to ldos? input is helpful for load transient. power input of ldo can be connected to main power supply. however, for optimum efficiency and lower NCP6951B thermal dissipation, the lowest voltage available in the system is preferred. input voltage of each ldo should always be higher than v out + v ldodrop (v drop , ldo dropout voltage at maximum current). capacitor dc bias characteristics real capacitance of ceramic capacitor changes versus dc voltage. special care should be taken to dc bias effect in order to make sure that the real capacitor value is always higher than the minimum allowable capacitor value specified. pcb layout recommendation the high speed operation of the NCP6951B demands careful attention to board layout and component placement. to prevent electromagnetic interference (emi) problems and reduce voltage ripple of the device, any high current copper trace which see high frequency switching should be optimized. therefore, use short and wide traces for power current paths and for power ground tracks, power plane and ground plane are recommended if possible. both the inductor and input/output capacitor of each dc to dc converters are in the high frequency switching path where current flow may be discontinuous. these components should be placed as close to NCP6951B as possible to reduce parasitic inductance connection. also it is important to minimize the area of the switching nodes and use the ground plane under them to minimize cross?talk to sensitive signals and ics. it?s suggested to keep as complete of a ground plane under NCP6951B as possible. pgnd and agnd pin connection must be connected to the ground plane. care should be taken to avoid noise interference between pgnd and agnd. it is always good practice to keep the sensitive tracks such as feedback connection (fb1 / fb2) away from switching signal connections (sw1 / sw2) by laying the tracks on the other side or inner layers of pcb. pgnd2 sw 2 sw 2 vbst vout3 flsel flen fl vout 2 agnd agnd vbg vin1 scl hwen vout 4 vout 1 fb 1 sda vin2 pvin 1 sw1 pgnd 1 vout 5 0402 0402 04 02 04 02 0402 04 02 0603 dfe201610r 0603 0603 0402 060 3 dfe252012p figure 40. recommended pcb components placement thermal considerations careful attention must be paid to the power dissipation of the NCP6951B. the power dissipation is a function of efficiency and output power. hence, increasing the output power requires better components selection. care should be taken of ldo v drop , the larger it is, the higher dissipation it will bring to NCP6951B. keep a large copper plane under and close to NCP6951B is helpful for thermal dissipation. table 72. ordering informations device marking package shipping ? NCP6951Bfcct1g 6951b wlcsp24 (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NCP6951B www. onsemi.com 35 package dimensions wlcsp24, 2.57x1.65 case 567ja issue c seating plane 0.10 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max ??? millimeters a1 d 1.65 bsc e b 0.24 0.29 e 0.40 bsc 0.60 e d a b pin a1 reference e a 0.05 b c 0.03 c 0.05 c 24x b 4 c b a 0.10 c a a1 c 0.17 0.23 2.57 bsc 0.25 24x dimensions: millimeters *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.40 0.40 0.10 c 2x top view side view bottom view note 3 e a2 0.36 ref recommended package outline 123 pitch d pitch a1 a2 a3 detail a detail a die coat a3 0.02 ref e/2 e/2 56 on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp6951/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

▲Up To Search▲

Price & Availability of NCP6951B

	To Download NCP6951B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .